Transistors, such as field effect transistors (FETs), may be used on the periphery of a memory device. These transistors can be located between charge pumps and the string drivers of a memory device that provide voltages to access lines (e.g., word lines) coupled to memory cells and can be used in charge pump circuitry and for the string drivers. Such transistors may be referred to as pass transistors, for example.
Some memory devices may include stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, a stacked memory array may include a plurality of vertical strings (e.g., NAND strings) of memory cells, e.g., coupled in series, between a source and a data line, such as a bit line. For example, the memory cells at a common location (e.g., at a common vertical level) might be commonly coupled to an access line, such as a local access line (e.g., a local word line), that may in turn be selectively coupled to a driver by a pass transistor. For example, pass transistors might couple local access lines to voltage supply circuitry, such as global access lines (e.g., global word lines).
The term vertical may be defined, for example, as a direction that is perpendicular to a base structure, such as a surface of an integrated circuit die. It should be recognized the term vertical takes into account variations from “exactly” vertical due to routine manufacturing and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term vertical.
In some stacked memory arrays, the pass transistors might be located under (e.g., at a vertical level under) the memory array. However, as the number of memory cells in the vertical strings increases, the number of local access lines may increase, and thus the number of pass transistors that might be located under the memory array may also increase. This can lead to increases in the size of the memory device in order to accommodate the increased number of pass transistors.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing transistor configurations for use in memory devices with stacked memory arrays and other applications.